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ics854s058agi revision a october 29, 2012 1 ?2012 integrated device technology, inc. datasheet 8:1 differential-to-lvds clock multiplexer ICS854S058I general description the ICS854S058I is an 8:1 differe ntial-to-lvds clock multiplexer which can operate up to 2.5ghz. the ICS854S058I has 8 selectable differential clock inputs. the pclk, npclk input pairs can accept lvpecl, lvds, sstl or cml levels. the fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. the select pins have internal pulldown resistors. the sel2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects pclk0, npclk0). features ? high speed 8:1 differential multiplexer ? one differential lvds output pair ? eight selectable differential pclk, npclk input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, sstl, cml ? maximum output frequency: 2.5ghz ? translates any single ended input signal to lvds levels with resistor bias on npclkx input ? additive phase jitter, rms: 0.065ps (typical) ? part-to-part skew: 300ps (maximum) ? propagation delay: 600ps (maximum) ? supply voltage range: 3.135v to 3.465v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packaging 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pclk0 npclk0 pclk1 npclk1 v dd sel0 sel1 sel2 pclk2 npclk2 pclk3 npclk3 pclk7 npclk7 npclk6 pclk6 q v dd nq gnd pclk5 npclk5 pclk4 npclk4 sel2 sel1 sel0 pulldown pulldown pulldown q nq pclk0 npclk0 pclk1 npclk1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 pclk2 npclk2 pclk3 npclk3 pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pclk4 npclk4 pclk5 npclk5 pclk6 npclk6 pclk7 npclk7 pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown (default) pin assignment ICS854S058I 24-lead tssop, 173-mil 7.8mm x 4.4mm x 0.925mm package body g package top view block diagram
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 pclk0 input pulldown non-inverting differential lvpecl clock input. 2 npclk0 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 3 pclk1 input pulldown non-inverting differential lvpecl clock input. 4 npclk1 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 5, 20 v dd power positive supply pins. 6, 7, 8 sel0, sel1, sel2 input pulldown clock select input pins. lvcmos/lvttl interface levels. 9 pclk2 input pulldown non-inverting differential lvpecl clock input. 10 npclk2 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 11 pclk3 input pulldown non-inverti ng differential lvpecl clock input. 12 npclk3 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 13 npclk4 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 14 pclk4 input pulldown non-inverti ng differential lvpecl clock input. 15 npclk5 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 16 pclk5 input pulldown non-inverti ng differential lvpecl clock input. 17 gnd power power supply ground. 18, 19 nq, q output differential outp ut pair. lvds interface levels. 21 npclk6 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 22 pclk6 input pulldown non-inverti ng differential lvpecl clock input. 23 npclk7 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 24 pclk7 input pulldown non-inverti ng differential lvpecl clock input. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown pulldown resistor 75 k ? r vdd /2 rpullup/pulldown resistor 50 k ?
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 3 ?2012 integrated device technology, inc. table 3. clock input function table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c inputs outputs sel2 sel1 sel0 q nq 0 (default) 0 0 pclk0 npclk0 0 0 1 pclk1 npclk1 0 1 0 pclk2 npclk2 0 1 1 pclk3 npclk3 1 0 0 pclk4 npclk4 1 0 1 pclk5 npclk5 1 1 0 pclk6 npclk6 1 1 1 pclk7 npclk7 item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ? ja 85.1c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 66 ma
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 4 ?2012 integrated device technology, inc. table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4c. lvpecl differen tial dc char acteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sel[0:2] v dd = v in = 3.465v 150 a i il input low current sel[0:2] v dd = 3.465v, v in = 0v -10 a symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk[0:7], npclk[0:7] v dd = v in = 3.465v 150 a i il input low current pclk[0:7] v dd = 3.465v, v in = 0v -10 a npclk[0:7] v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.2 v v cmr common mode input voltage; note 1, 2 gnd + 1.2 v dd v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.375 v ? v os v os magnitude change 50 mv
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 5 ?2012 integrated device technology, inc. table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. all parameters measured ? 1.0ghz unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs on different devices oper ating at the same supply voltag es and with equal load conditio ns. using the same type of inputs on each device, the ou tputs are measured at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: q/nq output measured differentially. see parameter measurement information for mux isolation diagram. symbol parameter test conditio ns minimum typical maximum units f out output frequency 2.5 ghz t pd propagation delay; note 1 300 600 ps t jit(?) buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.065 ps tsk (pp) part-to-part skew; note 2, 3 300 ps tsk (i) input skew 50 ps t r / t f output rise/fall time 20% to 80% 75 250 ps mux isolation mux isolation; note 4 155.52mhz, v pp = 400mv 85 db
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 6 ?2012 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10k hz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". ssb phase noise dbc/hz offset from carrier frequency (hz) additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.065ps (typical)
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 7 ?2012 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit propagation delay output rise/fall time differential input level part-to-part skew input skew scope q nq 3.3v5% power supply +? float gnd v dd t pd q nq npclk[0:7] pclk[0:7] 20% 80% 80% 20% t r t f v od nq q v dd npclk[0:7] pclk[0:7] gnd v cmr cross points v pp t sk(pp) part 1 part 2 q nq q nq t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) npclky pclky nq q npclkx pclkx
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 8 ?2012 integrated device technology, inc. parameter measurement in formation, continued offset voltage setup mux isolation differential output voltage application information recommendations for unused input pins inputs: pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. lvcmos control pins all control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. out out lvds dc input ? v os / v os v dd amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 100 out out dc input v dd lvds
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 9 ?2012 integrated device technology, inc. lvpecl clock input interface the pclk /npclk accepts l vpecl, lvds, sstl and other differential signals. the differential signal must meet the v pp and v cmr input requirements. figures 1a to 1d show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 1a. pclk/npclk input driven by a 3.3v lvds driver figure 1c. pclk/npclk input driven by a 3.3v lvpecl driver figure 1e. pclk/npclk input driven by a cml driver figure 1b. pclk/npclk input driven by an sstl driver figure 1d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple figure 1f. pclk/npclk input driven by a built-in pullup cml driver pclk npclk vbb 3.3v lvpecl input r1 1k r2 1k 3.3v zo = 50 zo = 50 c1 c2 r5 100 lvds c3 0.1f r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk lvpecl input cml 3.3v zo = 50 zo = 50 3.3v 3.3v r1 50 r2 50 pclk npclk lvpecl input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120 r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 zo = 50 3.3v 3.3v lvpecl input c1 c2 pclk npclk 3.3v lvpecl input 3.3v zo = 50 zo = 50 r1 100 cml built-in pullup
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 10 ?2012 integrated device technology, inc. wiring the differential input to accept single-ended levels figure 2 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possibl e to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ende d signal driving differential input 3.3v lvds driver termination a general lvds interface is shown in figure 3. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 3. typical lvds driver termination r2 1k v dd clk_in r1 1k c1 0.1uf v_ref pclkx npclkx 3.3v lvds driver r1 100 ? + 3.3v 50 50 100 differential transmission line
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 11 ?2012 integrated device technology, inc. schematic example an application schematic example of ICS854S058I is shown in figure 4. the inputs can accept various types of differential signals. in this example, the inputs are driven by lvds drivers. the transmission lines are assumed to be 100 ? differential. the 100 ? matched loads termination should be located near the receivers. it is recommended at least one decoupling capacitor per power pin. the decoupling capacitor should be low esr and located as close as possible to the power pin. figure 4. ICS854S058I schematic example set logic input to '0' to logic input pins logic control input examples to logic input pins set logic input to '1' 100 ohm differential 100 ohm differential 100 ohm differential zo = 50 lvds lvds ru2 not install zo = 50 r1 100 ru1 1k lvds + - r3 100 zo = 50 rd2 1k c1 0.1u zo = 50 rd1 not install c2 0.1u zo = 50 zo = 50 vdd vdd u1 ics854s058 pclk0 1 npclk0 2 pclk1 3 npclk1 4 vdd 5 sel0 6 sel1 7 sel2 8 pclk2 9 npclk2 10 pclk3 11 npclk3 12 npclk4 13 pclk4 14 npclk5 15 pclk5 16 gnd 17 nq 18 q 19 vdd 20 pclk7 24 npclk7 23 pclk6 22 npclk6 21 vdd vdd vdd=3.3v r2 100
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 12 ?2012 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS854S058I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S058I is the sum of the core power plus the power dissipation in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 66ma = 228.7mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 85.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.229w * 85.16c/w = 104.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 24 lead tssop, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 85.1c/w 79.7c/w 76.5c/w
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 13 ?2012 integrated device technology, inc. reliability information table 7. ? ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ICS854S058I is: 446 this device is pin and function compatib le, and a suggested replacement for ics854058. package outline and package dimensions package outline - g suffix for 24 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 85.1c/w 79.7c/w 76.5c/w all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 14 ?2012 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 854s058agilf ics854s058ail ?lead-free? 24 lead tssop tube -40 ? c to 85 ? c 854s058agilft ics854s058ail ?lead-free? 24 lead tssop tape & reel -40 ? c to 85 ? c
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer ics854s058agi revision a october 29, 2012 15 ?2012 integrated device technology, inc. revision history sheet rev table page description of change date a t10 1 9 16 deleted hiperclocks logo. updated gd paragraph to include cml. added cml to 3rd bullet. added figures 1e and 1f. deleted quantity from tape and reel. 10/29/12
ICS854S058I datasheet 8:1, differential-to-lvds clock multiplexer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discre tion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of idt?s products for any par ticular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reas onably expected to signif- icantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the id t logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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